Phase shift adjusting method and circuit
US7836386B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2006 |
| Grant date | Nov 16, 2010 |
| Priority date | — |
| Expiry date | Sep 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have respective phase shifts relative to the clock signal. An error detection code is calculated from first and second received data carried by the transmitted signals. The error detection code is transmitted from the receiving device to the sending device. An estimated first received data is calculated from the error detection code, wherein the estimated first received data are calculated under the assumption that the second received data are identical to the second test data. The first phase shift is adjusted on the basis of a comparison of the estimated first received data and the first test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.