Word line to bit line spacing method and apparatus

US7838928B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Werner Graf · Chur, CH
• Lars Heineck · Dresden, DE
• Martin Popp · Dresden, DE

Key dates

• Filing date: Jun 6, 2008
• Grant date: Nov 23, 2010
• Expiry date: Jun 6, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.