Inventor · Dresden, DE

Lars Heineck

40Patents
7h-index
74Co-inventors
72Inventor score

Filing activity: Apr 6, 1998 → Sep 19, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6342452B1 Method of fabricating a Si3N4/polycide structure using a dielectric sacrificial layer as a mask Electricity 31 Expired
US9881924B2 Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same Electricity 15 Active
US8772848B2 Circuit structures, memory circuitry, and methods Electricity 12 Active
US8569831B2 Integrated circuit arrays and semiconductor constructions Electricity 10 Active
US6919255B2 Semiconductor trench structure Electricity 10 Expired
US7274060B2 Memory cell array and method of forming the same Electricity 8 Expired
US7094674B2 Method for production of contacts on a wafer Electricity 7 Expired
US10566332B2 Semiconductor devices Electricity 7 Active
US6423607B1 Trench capacitor with insulation collar and corresponding fabrication method Electricity 7 Expired
US5998254A Method for creating a conductive connection between at least two zones of a first conductivity type Electricity 7 Expired
US6281079A MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and production process Electricity 6 Expired
US6916721B2 Method for fabricating a trench capacitor with an insulation collar Electricity 5 Expired
US9691773B2 Silicon buried digit line access device and method of forming the same Electricity 5 Active
US7018781B2 Method for fabricating a contact hole plane in a memory module Electricity 5 Expired
US8361856B2 Memory cells, arrays of memory cells, and methods of forming memory cells Electricity 5 Active
US9385132B2 Arrays of recessed access devices, methods of forming recessed access gate constructions, and methods of forming isolation gate constructions in the fabrication of recessed access devices Electricity 4 Active
US7838928B2 Word line to bit line spacing method and apparatus Electricity 4 Active
US10163909B2 Methods for fabricating a semiconductor memory device Electricity 4 Active
US7012313B2 MOS transistor in a single-transistor memory cell having a locally thickened gate oxide Electricity 3 Expired
US9337201B2 Memory cells, arrays of memory cells, and methods of forming memory cells Electricity 3 Active
US11488981B2 Array of vertical transistors and method used in forming an array of vertical transistors Electricity 2 Active
US9012330B2 Method for semiconductor cross pitch doubled patterning process Electricity 2 Active
US9070584B2 Buried digitline (BDL) access device and memory array Electricity 2 Active
US8735267B1 Buried word line structure and method of forming the same Electricity 2 Active
US7087492B2 Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate Electricity 2 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.