Integrated circuit and a method for recovering from a low-power period
US7839207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Nov 25, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/144
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit, including: (i) a power gated circuit which power supply is shut down during a low-power period; (ii) a retention circuit, coupled to the power gated circuit during at least a portion of a non-low-power period, the retention circuit is adapted to store, during the low-power period, state information reflecting a state of the power gated circuit before the low-power period started; (iii) a first portion of the power grid, coupled to the retention circuit and to a first end of a power supply switch, adapted to provide to the retention circuit a supply voltage during the low-power period and during a non-low-power period; wherein the power supply switch is open during the low-power period and is closed during the non-low-power period; and (iv) a second portion of the power grid, coupled to a second end of the power supply switch and to the power gated circuit; adapted to supply a gated supply voltage to the power gated circuit during the non-low-power period. The first portion of the power grid is characterized by intrinsic capacitance that is larger that the intrinsic capacitance of the second portion of the power grid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.