Push-pull FPGA cell
US7839681B2 · kind B2 · utility
18Cited by
19References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2008 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Jun 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.