Patent · US Active

Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer

US7839693B1 · kind B1 · utility

0Cited by

4References

17Claims

0Family size

Assignee

XILINIX, INC. · US

Inventors

Sunhom Paak · Saratoga, US
Boon Yong Ang · Cupertino, US
Hsung Jai Im · San Jose, US
Daniel Gitlin · Palo Alto, US

Key dates

Filing date	Jan 7, 2010
Grant date	Nov 23, 2010
Priority date	—
Expiry date	Jan 7, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/0466
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.