Daniel Gitlin
18Patents
10h-index
28Co-inventors
68Inventor score
Filing activity: Apr 22, 1997 → Jul 30, 2010
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5880620A | Pass gate circuit with body bias control | Electricity | 187 | Expired |
| US6266269A | Three terminal non-volatile memory element | Physics | 89 | Expired |
| US6621325B2 | Structures and methods for selectively applying a well bias to portions of a programmable device | Electricity | 61 | Expired |
| US7032194B1 | Layout correction algorithms for removing stress and other physical effect induced process deviation | Physics | 50 | Expired |
| US6268639A | Electrostatic-discharge protection circuit | Emerging Cross-Sectional Technologies | 32 | Expired |
| US5870327A | Mixed mode RAM/ROM cell using antifuses | Physics | 19 | Expired |
| US7294888B1 | CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer | Physics | 15 | Expired |
| US6645802B1 | Method of forming a zener diode | Emerging Cross-Sectional Technologies | 14 | Expired |
| US6549458B1 | Non-volatile memory array using gate breakdown structures | Physics | 14 | Expired |
| US6522582B1 | Non-volatile memory array using gate breakdown structures | Physics | 13 | Expired |
| US6740936B1 | Ballast resistor with reduced area for ESD protection | Electricity | 9 | Expired |
| US7936006B1 | Semiconductor device with backfilled isolation | Electricity | 4 | Active |
| US7772093B2 | Method of and circuit for protecting a transistor formed on a die | Electricity | 2 | Active |
| US8436656B2 | Method and apparatus for saving power in an integrated circuit | Electricity | 1 | Active |
| US7688639B1 | CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer | Physics | 0 | Active |
| US7956385B1 | Circuit for protecting a transistor during the manufacture of an integrated circuit device | Electricity | 0 | Active |
| US7839693B1 | Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer | Physics | 0 | Active |
| US7687797B1 | Three-terminal non-volatile memory element with hybrid gate dielectric | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.