Techniques for storing instructions and related information in a memory hierarchy
US7840786B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2007 |
| Grant date | Nov 23, 2010 |
| Priority date | — |
| Expiry date | Oct 18, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information. The first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information, which corresponds to an uncompressed version of the first predecode information, for storage in the third memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.