Double DRAM bit steering for multiple error corrections

US7840860B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Luiz C. Alves · Hopewell Junction, US
• Mark A. Brittain · Pflugerville, US
• Timothy J. Dell · Colchester, US
• Sanjeev Ghai · Round Rock, US
• Warren E. Maule · Cedar Park, US
• Scott Barnett Swaney · Catskill, US

Key dates

• Filing date: Aug 7, 2008
• Grant date: Nov 23, 2010
• Expiry date: Aug 7, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/0409
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.