Sanjeev Ghai
65Patents
10h-index
35Co-inventors
78Inventor score
Filing activity: Jun 24, 1999 → Jan 10, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7934070B2 | Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices | Emerging Cross-Sectional Technologies | 72 | Active |
| US7337293B2 | Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices | Physics | 57 | Expired |
| US6408362B1 | Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data | Physics | 51 | Expired |
| US6282615A | Multiprocessor system bus with a data-less castout mechanism | Physics | 41 | Expired |
| US6345341B1 | Method of cache management for dynamically disabling O state memory-consistent data | Physics | 24 | Expired |
| US7130967B2 | Method and system for supplier-based memory speculation in a memory subsystem of a data processing system | Physics | 24 | Expired |
| US6405290B1 | Multiprocessor system bus protocol for O state memory-consistent data | Physics | 23 | Expired |
| US7467323B2 | Data processing system and method for efficient storage of metadata in a system memory | Physics | 19 | Expired |
| US6397303B1 | Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines | Physics | 18 | Expired |
| US6442653B1 | Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data | Physics | 15 | Expired |
| US7058767B2 | Adaptive memory access speculation | Physics | 9 | Expired |
| US8892821B2 | Method and system for thread-based memory speculation in a memory subsystem of a data processing system | Physics | 8 | Active |
| US6349368B1 | High performance mechanism to support O state horizontal cache-to-cache transfers | Physics | 8 | Expired |
| US6904490B2 | Method and system of managing virtualized physical memory in a multi-processor system | Physics | 8 | Expired |
| US6970936B2 | Data processing system and method of communication that employ a request-and-forget protocol | Physics | 8 | Expired |
| US7840860B2 | Double DRAM bit steering for multiple error corrections | Physics | 8 | Active |
| US7523364B2 | Double DRAM bit steering for multiple error corrections | Physics | 8 | Active |
| US6539487B1 | System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks | Emerging Cross-Sectional Technologies | 7 | Expired |
| US8930629B2 | Data cache block deallocate requests in a multi-level cache hierarchy | Physics | 7 | Active |
| US6467030B1 | Method and apparatus for forwarding data in a hierarchial cache memory architecture | Physics | 7 | Expired |
| US6907494B2 | Method and system of managing virtualized physical memory in a memory controller and processor system | Physics | 6 | Expired |
| US6678814B2 | Method and apparatus for allocating data usages within an embedded dynamic random access memory device | Physics | 6 | Expired |
| US7017024B2 | Data processing system having no system memory | Emerging Cross-Sectional Technologies | 6 | Expired |
| US9032157B2 | Virtual machine failover | Physics | 5 | Active |
| US9336142B2 | Cache configured to log addresses of high-availability data via a non-blocking channel | Physics | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.