Method of manufacturing a semiconductor power device

US7842574B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Giuseppe Arena · Messina, IT
• Caterina Donato · Altofonte, IT
• Cateno Marco Camalleri · Catania, IT
• Angelo Magri · Mascalucia, IT

Key dates

• Filing date: Jan 8, 2008
• Grant date: Nov 30, 2010
• Expiry date: Jun 16, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

A trench is formed in a semiconductor body, the side walls and the bottom of the trench covered with a first dielectric material layer, the trench filled with a second dielectric material layer, the first and the second dielectric material layers are etched via a partial, simultaneous, and controlled etching such that the dielectric materials have similar etching rates, a gate-oxide layer having a thickness smaller than the first dielectric material layer deposited on the walls of the trench, a gate region of conductive material formed within the trench, and body regions and source regions formed within the semiconductor body at the sides of and insulated from the gate region. Thereby, the gate region extends only on top of the remaining portions of the first and second dielectric material layers.