Method of forming small pitch pattern using double spacers
US7842601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2006 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Mar 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0338
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a small pitch pattern using double spacers is provided. A material layer and first hard masks are used and characterized by a line pattern having a smaller line width than a separation distance between adjacent mask elements. A first spacer layer covering sidewall portions of the first hard mask and a second spacer layer are formed, and spacer-etched, thereby forming a spacer pattern-shaped second hard mask on sidewall portions of the first hard mask. A portion of the first spacer layer between the first hard mask and the second hard mask is selectively removed. The material layer is selectively etched using the first and second hard masks as etch masks, thereby forming the small pitch pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.