Fully isolated high-voltage MOS device
US7843002B2 · kind B2 · utility
6Cited by
9References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 3, 2007 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Aug 15, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A semiconductor structure includes a semiconductor substrate; an n-type tub extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the n-type tub comprises a bottom buried in the semiconductor substrate; a p-type buried layer (PBL) on a bottom of the tub, wherein the p-type buried layer is buried in the semiconductor substrate; and a high-voltage n-type metal-oxide-semiconductor (HVNMOS) device over the PBL and within a region encircled by sides of the n-type tub.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.