Electronic parts packaging structure
US7843059B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2006 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | May 6, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.