Signal termination scheme for high speed memory modules
US7843213B1 · kind B1 · utility
8Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2009 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | May 21, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is coupled to a subset of lines of a data input/output (I/O) bus. The memory device includes an on-die active termination circuit for terminating the subset of lines of the data I/O bus with a selected impedance being one of a plurality of selectable impedances; a termination value register being coupled to the on-die active termination circuit for storing a value representing the selected impedance; and a termination value setting circuit being coupled to the termination value register, for setting the value representing the selected impedance in the termination value register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.