Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
US7844435B2 · kind B2 · utility
1Cited by
9References
5Claims
0Family size
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Key dates
| Filing date | Nov 19, 2007 |
| Grant date | Nov 30, 2010 |
| Priority date | — |
| Expiry date | Oct 19, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip has new Frequency dependent RLC extraction and modeling providing on chip integrity and noise verification and the extraction and modeling employs:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.