Structured, electrically-formed floating gate for flash memories
US7847333B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Mar 25, 2008 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Nov 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Semiconductor memory devices and methods to fabricate thereof are described. A first gate base is formed on a first insulating layer on a substrate. A first gate fin is formed on the first gate base. The first gate fin has a top and sidewalls. Next, a second insulating layer is formed on the top and sidewalls of the first gate fin and portions of the first gate base. A second gate is formed on the second insulating layer. Source and drain regions are formed in the substrate at opposite sides of the first gate base. In one embodiment, the first gate fin includes an undoped polysilicon and the first gate base includes an n-type polysilicon. In another embodiment, the first gate fin includes an undoped amorphous silicon and the first gate base includes an n-type amorphous silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.