Non-volatile memory cell array and logic

US7847374B1 · kind B1 · utility

Inventor

• Chih-Hsin Wang · San Jose, US

Key dates

• Filing date: Jul 7, 2008
• Grant date: Dec 7, 2010
• Expiry date: Aug 18, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B63/10

Abstract

A semiconductor device comprising a memory region including one or more transistor string arrays, a logic region including one or more logic transistors and an isolation region for isolating the logic transistors. The string array includes a plurality, T, of bipolar junction transistors. The string array includes a common collector region for the T bipolar junction transistors, a common base region for the T bipolar junction transistors, a plurality of emitters, one emitter for each of the T bipolar junction transistors, a number, B, of base contacts for the T bipolar junction transistors where the base contacts electrically couple the common base region and where the number of base contacts, B, is less than the number of transistors, T.