Overlay measurement target
US7847939B2 · kind B2 · utility
10Cited by
18References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 22, 2008 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | May 22, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.