Patent · US Active

High speed memory architecture

US7848153B2 · kind B2 · utility

8Cited by

2References

30Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Bruennert · Munich, DE
Peter Gregorius · Munich, DE
Georg Braun · Hersbruck, DE
Andreas Gaertner · Munich, DE
Hermann Ruckerbauer · Radolfzell, DE
George Alexander · Durham, US
Johannes Stecker · Birkenfeld, DE

Key dates

Filing date	Aug 19, 2008
Grant date	Dec 7, 2010
Priority date	—
Expiry date	Feb 21, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Memory devices and memory modules are disclosed. In one embodiment, a memory device includes a semiconductor substrate having a first edge and a second edge opposed to the first edge. A plurality of memory banks is disposed at a central portion of the semiconductor substrate, each memory bank including a plurality of memory cells. A plurality of input/output contacts is disposed between the first edge and the memory banks. Delay locked loop circuitry is disposed adjacent the first edge. A plurality of address and command contacts is disposed between the second edge and the memory banks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.