Reduced-delay clocked logic
US7849349B2 · kind B2 · utility
8Cited by
4References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Dec 7, 2010 |
| Priority date | — |
| Expiry date | Oct 1, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/03
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delay in a clocked logic circuit is reduced by partially determining a next state of the clocked logic circuit based on a current state of the clocked logic circuit during a first portion of a clock cycle. The partially determined next state of the clocked logic circuit is prevented from affecting the current state of the clocked logic circuit during the first portion of the clock cycle. The next state of the clocked logic circuit is completely determined based on a previous state of the clocked logic circuit and the partially determined next state of the clocked logic circuit during a second portion of the clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.