Method for fabricating transistor in a semiconductor device utilizing an etch stop layer pattern as a dummy pattern for the gate electrode formation
US7851298B2 · kind B2 · utility
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1References
8Claims
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Key dates
| Filing date | Oct 28, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Oct 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/053
Abstract
Provided is a method for fabricating a transistor in a semiconductor device. The method includes forming an etch stop layer pattern over a semiconductor substrate; forming a semiconductor layer for covering the etch stop layer pattern; forming a recess trench that exposes an upper surface of the etch stop layer pattern by etching the semiconductor layer pattern; removing the etch stop layer pattern exposed in the recess trench; and forming a gate that fills the recess trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.