Bonding metallurgy for three-dimensional interconnect
US7851346B2 · kind B2 · utility
19Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Jul 21, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Jan 2, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.