Inventor · Taipei, TW

Bo-I Lee

21Patents
6h-index
21Co-inventors
65Inventor score

Filing activity: Jul 21, 2008 → Jun 15, 2020

Most-cited inventions

PatentTitleAreaCited byStatus
US9275924B2 Semiconductor package having a recess filled with a molding compound Electricity 59 Active
US8803332B2 Delamination resistance of stacked dies in die saw Electricity 26 Active
US7851346B2 Bonding metallurgy for three-dimensional interconnect Electricity 19 Active
US8426256B2 Method of forming stacked-die packages Electricity 19 Active
US8743561B2 Wafer-level molded structure for package assembly Electricity 7 Active
US7687311B1 Method for producing stackable dies Electricity 6 Active
US10857649B2 Method and apparatus for performing a polishing process in semiconductor fabrication Performing Operations; Transporting 3 Active
US8932906B2 Through silicon via bonding structure Electricity 3 Active
US9403254B2 Methods for real-time error detection in CMP processing Performing Operations; Transporting 3 Active
US9138861B2 CMP pad cleaning apparatus Performing Operations; Transporting 3 Active
US9406632B2 Semiconductor package including a substrate with a stepped sidewall structure Electricity 3 Active
US8242611B2 Bonding metallurgy for three-dimensional interconnect Electricity 2 Active
US9117939B2 Method of forming wafer-level molded structure for package assembly Electricity 2 Active
US9754917B2 Method of forming wafer-level molded structure for package assembly Electricity 1 Active
US9242342B2 Manufacture and method of making the same Performing Operations; Transporting 0 Active
US11413722B2 Apparatus and method for chemically mechanically polishing Emerging Cross-Sectional Technologies 0 Active
US11690737B2 Stent using wireless transmitted power and external operating apparatus thereof Human Necessities 0 Active
US9570368B2 Method of manufacturing semiconductor package including forming a recessed region in a substrate Electricity 0 Active
US9673174B2 Through silicon via bonding structure Electricity 0 Active
US10668592B2 Method of planarizing a wafer Performing Operations; Transporting 0 Active
US10163710B2 Method of manufacturing semiconductor device by applying molding layer in substrate groove Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.