Insulated gate e-mode transistors
US7851825B2 · kind B2 · utility
105Cited by
1References
33Claims
0Family size
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Key dates
| Filing date | Nov 26, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Feb 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
Enhancement-mode III-nitride transistors are described that have a large source to drain barrier in the off state, low off state leakage, and low channel resistance in the access regions are described. The devices can include a charge depleting layer under the gate and/or a charge enhancing layer outside of the gate region, that is, in the access region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.