Microelectronic package and method of cooling an interconnect feature in same
US7851905B2 · kind B2 · utility
40Cited by
33References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Feb 28, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/93
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package comprises a substrate (110, 310), a die (320) supported by the substrate, an interconnect feature (130, 230, 330) connecting the die and the substrate to each other, and a thermoelectric cooler (140, 170, 240, 340) adjacent to the interconnect feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.