Receiver circuit of semiconductor memory apparatus
US7852131B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Jun 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver circuit capable of controlling setup/hold time includes a first phase transmission unit configured to generate a first output signal by detecting input data according to plural detection levels while being synchronized with a first clock signal, and controlling setup/hold time of the first output signal based on a level of a first offset voltage, a level converter configured to control a voltage level of the first output signal according to a first code, and a second phase transmission unit configured to receive an output signal of the level converter for as a second offset voltage while being synchronized with a second clock signal, to generate a second output signal by detecting the input data according to the detection levels, and to control setup/hold time of the second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.