Sigma-delta modulator with digitally filtered delay compensation
US7852249B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2009 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Apr 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus are provided for continuous-time sigma-delta modulators. The sigma-delta modulator comprises an input node for an input signal and a quantizer configured to convert an analog signal to a digital value. A main feedback arrangement is coupled to the quantizer and configured to delay the digital value by a first delay period and generate a main feedback signal by digitally filtering the first delayed value. A compensation feedback arrangement is coupled to the quantizer and configured to delay the digital value by a second delay period, wherein the second delay period is not influenced by the first delay period, and generate a compensation feedback signal by digitally filtering the second delayed value. A forward signal arrangement produces the analog signal based on the input signal, the main feedback signal, and the compensation feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.