Scalable shader architecture

US7852340B2 · kind B2 · utility

Assignee

• NVIDIA Corporation · US

Inventors

• Rui M. Bastos · Santa Clara, US
• Karim M. Abdalla · Menlo Park, US
• Christian Rouet · San Rafael, US
• Michael J. M. Toksvig · Palo Alto, US
• Johnny S. Rhoades · Durham, US
• Roger L. Allen · San Jose, US
• John Douglas Tynefield, Jr. · Los Altos, US
• Emmett M. Kilgariff · San Jose, US
• Gary M. Tarolli · Concord, US
• Brian Keith Cabral · San Jose, US
• Craig M. Wittenbrink · Palo Alto, US
• Sean J. Treichler · Sunnyvale, US

Key dates

• Filing date: Dec 14, 2007
• Grant date: Dec 14, 2010
• Expiry date: Apr 20, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A scalable shader architecture is disclosed. In accord with that architecture, a shader includes multiple shader pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines can be functionally removed as required, thus preventing a defective shader pipeline from causing a chip rejection. The shader includes a shader distributor that processes rasterized pixel data and then selectively distributes the processed rasterized pixel data to the various shader pipelines, beneficially in a manner that balances workloads. A shader collector formats the outputs of the various shader pipelines into proper order to form shaded pixel data. A shader instruction processor (scheduler) programs the individual shader pipelines to perform their intended tasks. Each shader pipeline has a shader gatekeeper that interacts with the shader distributor and with the shader instruction processor such that pixel data that passes through the shader pipelines is controlled and processed as required.