Write-assist SRAM cell
US7852661B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2008 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Jun 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a word-line; a column select line; and a latch. The latch includes a first storage node and a second storage node complementary to each other; and an operation voltage node. A control circuit is coupled between the operation voltage node and the latch. The control circuit includes a first input coupled to the word-line; and a second input coupled to the column selection line. The control circuit is configured to interconnect the operation voltage node and the latch when both the word-line and the column select line are selected, and disconnect the operation voltage node and the latch when at least one of the word-line and the column select line is not selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.