Suspend mode operation for reduced power
US7853811B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2006 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (300) includes a suspend circuit that includes a first input to receive a suspend signal, a first output to generate an awake signal, and outputs to provide control signals to various integrated circuit resources. During suspend mode, the suspend circuit suspends operation of the integrated circuit resources by driving its output pins to one of a plurality of predefined state selected by corresponding mode select signals and by locking its synchronous elements to known states. Upon termination of suspend mode, the circuit re-activates the integrated circuit resources according to a user-defined timing schedule. The user-defined timing schedule and the mode select signals may be provided to the integrated circuit during its configuration as part of a configuration bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.