Method and apparatus for performing path-level skew optimization and analysis for a logic design
US7853911B1 · kind B1 · utility
7Cited by
18References
36Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Dec 14, 2010 |
| Priority date | — |
| Expiry date | Nov 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.