Planar and non-planar CMOS devices with multiple tuned threshold voltages
US7855105B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2009 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Jun 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.