Vijay Narayanan
256Patents
19h-index
234Co-inventors
89Inventor score
Filing activity: Jul 5, 2001 → Feb 21, 2025
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9748145B1 | Semiconductor devices with varying threshold voltage and fabrication methods thereof | Electricity | 464 | Active |
| US6921711B2 | Method for forming metal replacement gate of high performance | Electricity | 119 | Expired |
| US7488656B2 | Removal of charged defects from metal oxide-gate stacks | Electricity | 73 | Expired |
| US6982230B2 | Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures | Electricity | 65 | Expired |
| US9997519B1 | Dual channel structures with multiple threshold voltages | Electricity | 61 | Active |
| US7105889B2 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics | Electricity | 61 | Expired |
| US7855105B1 | Planar and non-planar CMOS devices with multiple tuned threshold voltages | Electricity | 60 | Active |
| US7242055B2 | Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide | Electricity | 38 | Expired |
| US7432567B2 | Metal gate CMOS with at least a single gate metal and dual gate dielectrics | Electricity | 37 | Active |
| US6852575B2 | Method of forming lattice-matched structure on silicon and structure formed thereby | Electricity | 35 | Expired |
| US7696036B2 | CMOS transistors with differential oxygen content high-k dielectrics | Electricity | 26 | Active |
| US7479683B2 | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics | Electricity | 25 | Expired |
| US7071122B2 | Field effect transistor with etched-back gate dielectric | Electricity | 25 | Expired |
| US7989902B2 | Scavenging metal stack for a high-k gate dielectric | Electricity | 24 | Active |
| US7718496B2 | Techniques for enabling multiple Vt devices using high-K metal gate stacks | Electricity | 24 | Active |
| US7838908B2 | Semiconductor device having dual metal gates and method of manufacture | Electricity | 23 | Active |
| US7870151B2 | Fast accurate fuzzy matching | Physics | 22 | Active |
| US8110467B2 | Multiple Vt field-effect transistor devices | Electricity | 21 | Active |
| US7863126B2 | Fabrication of a CMOS structure with a high-k dielectric layer oxidizing an aluminum layer in PFET region | Electricity | 20 | Active |
| US9793397B1 | Ferroelectric gate dielectric with scaled interfacial layer for steep sub-threshold slope field-effect transistor | Electricity | 18 | Active |
| US8741713B2 | Reliable physical unclonable function for device authentication | Electricity | 18 | Active |
| US7655994B2 | Low threshold voltage semiconductor device with dual threshold voltage control means | Electricity | 17 | Expired |
| US7067422B2 | Method of forming a tantalum-containing gate electrode structure | Electricity | 17 | Expired |
| US8420473B2 | Replacement gate devices with barrier metal for simultaneous processing | Electricity | 16 | Active |
| US7750418B2 | Introduction of metal impurity to change workfunction of conductive electrodes | Electricity | 16 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.