Asymmetric sense-amp flip-flop
US7855587B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 30, 2007 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Jun 16, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An Asymmetric Sense-Amp Flip-Flop (ASAFF) is disclosed that may achieve zero setup time and short clock-to-Q delays. The ASAFF captures input data at a clock transition by setting values of a first node and a second node in a manner that is input data value dependent. If the input data is at the first input data value, the first node is set and held at a first storage value after a first delay, and the second node is set and held at a second storage value after a second delay, and if the input data is at a second input data value, the first node is set and held at a third storage value after a third delay, and the second node is set and held at a fourth storage value, after a fourth delay. This internal-path dependent difference in delay enables ASAFF to achieve zero setup time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.