Power-on management circuit for memory
US7855930B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 2009 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Jul 10, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-on management circuit for a memory device is provided. The power-on management circuit comprises a first external power-on voltage detector, a second external power-on voltage detector, a delay unit, a logic circuit, an internal power-on voltage detector, a voltage control circuit, a plurality of first electric pumps and a second electric pump. The first external power-on voltage detector has a first voltage threshold, receives a first external voltage, and generates a first control signal when the first external voltage is higher than the first voltage threshold. The second external power-on voltage detector has a second voltage threshold, receives a second external voltage, and generates a second control signal when the second external voltage is higher than the second voltage threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.