Clock synchronization circuit and operation method thereof
US7855933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2008 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Mar 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.