Strobe technique for test of digital signal timing
US7856578B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2005 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Aug 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.