Patent · US Active

Method for self-aligned doubled patterning lithography

US7856613B1 · kind B1 · utility

25Cited by

1References

15Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Milind Weling · San Jose, US
Judy Huckabay · Fremont, US
Abdurrahman Sezginer · Ridgefield, US

Key dates

Filing date	Nov 4, 2008
Grant date	Dec 21, 2010
Priority date	—
Expiry date	Dec 1, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG03F1/00
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Various embodiments of the invention provide systems and methods for semiconductor device fabrication and generation of photomasks for patterning a target layout of line features and large features. Embodiments of the invention are directed towards systems and methods using self-aligned double pattern to define the target layout of line features and large features.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.