Dynamic address windowing on a PCI bus
US7856635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Dec 21, 2010 |
| Priority date | — |
| Expiry date | Feb 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.