Independently controlled, double gate nanowire memory cell with self-aligned contacts
US7859028B2 · kind B2 · utility
3Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2009 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Feb 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
Abstract
A double gate, dynamic storage device and method of fabrication are disclosed. A back (bias gate) surrounds three sides of a semiconductor body with a front gate disposed on the remaining surface. Two different gate insulators and gate materials may be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.