Three-terminal single poly NMOS non-volatile memory cell
US7859043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2009 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jun 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.