Shielded gate trench FET with the shield and gate electrodes connected together in non-active region
US7859047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 11, 2008 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Apr 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A field effect transistor (FET) includes a plurality of trenches extending into a semiconductor region. Each trench includes a gate electrode and a shield electrode with an inter-electrode dielectric therebetween. A body region extends between each pair of adjacent trenches, and source regions extend in each body region adjacent to the trenches. A first interconnect layer contacts the source and body regions. The plurality of trenches extend in an active region of the FET, and the shield electrode and gate electrode extend out of each trench and into a non-active region of the FET where the shield electrodes and gate electrodes are electrically connected together by a second interconnect layer. The electrical connection between the shield and gate electrodes is made through periodic contact openings formed in a gate runner region of the non-active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.