Structure and method for biasing phase change memory array for reliable writing
US7859884B2 · kind B2 · utility
113Cited by
17References
20Claims
0Family size
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Key dates
| Filing date | Oct 31, 2007 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Jun 10, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.