Semiconductor device
US7859896B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2006 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Mar 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.