Methods and structures for reading out non-volatile memory using NVM cells as a load element
US7859903B1 · kind B1 · utility
5Cited by
1References
30Claims
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Key dates
| Filing date | Feb 14, 2008 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Apr 15, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.