Patent · US Active

Providing a set aside mechanism for posted interrupt transactions

US7861024B2 · kind B2 · utility

7Cited by

2References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Bryan R. White · Folsom, US
Douglas R. Moran · Folsom, US

Key dates

Filing date	Sep 30, 2008
Grant date	Dec 28, 2010
Priority date	—
Expiry date	Jan 9, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F1/3203
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, a method includes receiving an incoming posted transaction in a processor complex from a peripheral device, determining if the transaction is an interrupt transaction, and if so routing it to a first queue, and otherwise routing it to a second queue. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.