Second chance replacement mechanism for a highly associative cache memory of a processor
US7861041B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2007 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | May 28, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory system includes a cache memory and a block replacement controller. The cache memory may include a plurality of sets, each set including a plurality of block storage locations. The block replacement controller may maintain a separate count value corresponding to each set of the cache memory. The separate count value points to an eligible block storage location within the given set to store replacement data. The block replacement controller may maintain for each of at least some of the block storage locations, an associated recent access bit indicative of whether the corresponding block storage location was recently accessed. In addition, the block replacement controller may store the replacement data within the eligible block storage location pointed to by the separate count value depending upon whether a particular recent access bit indicates that the eligible block storage location was recently accessed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.