Method and system for on-chip configurable data ram for fast memory and pseudo associative caches
US7861055B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 2005 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | Dec 20, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a method and system for an on-chip configurable data RAM for fast memory and pseudo associative caches are provided. Memory banks of configurable data RAM integrated within a chip may be configured to operate as fast on-chip memory or on-chip level 2 cache memory. A set associativity of the on-chip level 2 cache memory may be same after configuring the memory banks as prior to the configuring. The configuring may occur during initialization of the memory banks, and may adjusted the amount of the on-chip level 2 cache. The memory banks configured to operate as on-chip level 2 cache memory or as fast on-chip memory may be dynamically enabled by a memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.