Power-driven timing analysis and placement for programmable logic
US7861190B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 2005 |
| Grant date | Dec 28, 2010 |
| Priority date | — |
| Expiry date | May 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.